
AMD Epyc 'Venice' will be built on TSMC's N2 node, 5th-gen Epyc to be fabbed in Arizona
In a nutshell: The 6th-generation AMD Epyc processors, codenamed Venice, will be the first high-performance computing product built using TSMC's 2nm (N2) process node. Team Red also confirmed that TSMC's new Fab 21 facility in Arizona has …